发明名称
摘要 The invention provides a semiconductor device in the form of an LSI circuit having a large number of terminals wherein an increase of the number of pad terminals for a power source potential and wherein a ground potential does not increase the inductances of wiring lines to the pad terminals and the terminals are arranged efficiently. The semiconductor device includes a semiconductor chip having a semiconductor substrate on which a first pad arrangement region, a buffer arrangement region and a second pad arrangement region are successively assured in this order toward the outer side around an internal circuit formation region and arranged in parallel to each other. A first power source pad and a first grounding pad for an internal circuit are provided in the first pad arrangement region while a plurality of pads for inputting and/or outputting signals are provided in the second pad region. The pads are bonding connected by respective thin metal lines to external lead terminals provided on a support.
申请公布号 JP2674553(B2) 申请公布日期 1997.11.12
申请号 JP19950072812 申请日期 1995.03.30
申请人 发明人
分类号 H01L21/60;H01L23/50;H01L23/552;H01L27/02 主分类号 H01L21/60
代理机构 代理人
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