发明名称 HOLD CONFIRMATION CIRCUIT FOR DATA MEMORY
摘要 PROBLEM TO BE SOLVED: To obtain a hold confirmation circuit by which the correlation accuracy between data inversion and power-supply change is enhanced by a method wherein a change in the content of data in a dummy cell part adjacent to a data memory which writes/reads out data via an internal bus is always monitored and an interrupt signal is output. SOLUTION: Respective dummy cells in a dummy cell part 11 which is constituted of a plurality of dummy cells jointly own bit lines in respective cells inside a data memory 2, they are connected to word lines which are parallel to respective word lines inside the memory 2, and they are connected to a VDD line and a GND line which are common to the respective cells inside the memory 2. Consequently, the electric characteristic of the respective dummy cells can be brought close to the electric characteristic of the cells inside the memory 2. In addition, the respective dummy cells are written via an internal bus 3, and an initial value is set. A dummy-cell monitoring circuit 12 is provided with a parity computing part and with a logic element, it computes the parity of the dummy cells inside the cell part 11, and it detects a change in the content of data. The logic element, to which the output signal of the computing part is input, output an interrupt signal when the change in the content of the data in the respective dummy cells inside the cell part 11 is detected.
申请公布号 JPH09293385(A) 申请公布日期 1997.11.11
申请号 JP19960105601 申请日期 1996.04.25
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 ISHIHARA KUNIYASU
分类号 G06F12/16;G06F11/00;G06F11/30;G11C16/02;G11C16/06;G11C17/00;G11C29/00;G11C29/12;G11C29/24 主分类号 G06F12/16
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