发明名称 SYNCHRONIZING SIGNAL DETECTION CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To avoid discrimination of a synchronizing signal pattern for a period other than a synchronizing signal period even when a bit error is caused in reception data. SOLUTION: A bit comparison section 2 compares reception data D1 received serially and a synchronizing signal pattern D2 generated by a synchronizing signal pattern generating section 1 for each bit to provide an output of a comparison result. A mismatching bit number count section 3 counts the bit number mismatched by the bit comparison in the unit of synchronizing signal patterns. A mismatching bit number comparison section 4 reads number of preceding mismatched bits (k) stored in a bit number storage section 5 and compares it with a mismatched bit number (m) received newly and provides an output of a control pulse P1 when a new mismatched bit number (m) is smaller, and updates the stored value (k) in the bit number storage section 5 with the mismatched bit number (m). A synchronizing timing signal generating section 6 generates a synchronizing timing signal while changing the leading time in response to the control pulse P1.</p>
申请公布号 JPH09294118(A) 申请公布日期 1997.11.11
申请号 JP19960106858 申请日期 1996.04.26
申请人 NEC SHIZUOKA LTD 发明人 MORITA KAZUO
分类号 H04L7/08;H04L7/04;H04Q7/14;(IPC1-7):H04L7/08 主分类号 H04L7/08
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