| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a clock changeover circuit in which production of a signal error due to a phase jump at an output is prevented after the end of initialization at application of power. SOLUTION: This circuit is provided with a power application state initializing section 12 to display a prescribed initializing period at application of power, a selection section 2 provides an output of a clock reception section 1 while receiving the initializing period indication signal and a selection section 5 provides an output of a 1/N frequency divider circuit section 4. A selection section 11 provides a digital clock supply clock with a prescribed frequency outputted from the clock reception section 1 while receiving the initializing period indication signal and an output clock outputted from a clock output section 8 in the case of the DCS clock mode to the 1/N frequency divider circuit section 4 respectively. The 1/N frequency divider circuit section 4 receives an extracted transmission line clock and provides an output of the result of 1/N frequency division of the block, while receiving the initializing period indication signal and receiving the DCS clock or the output clock with a prescribed frequency and providing an output of a clock whose phase is synchronously with the phase of the received clock.</p> |
