| 摘要 |
A semiconductor die attach arrangement which provides an increase in signal availability to and from the die without compromising the physical integrity of signal traces and integrity of the conducted signal. In a preferred embodiment, a circuit board includes a die-attach region surrounded by a boundary line that is spaced apart from the die-attach region, thereby defining an intermediate region which surrounds the die-attach region. Bond sites are arranged along the boundary line. In one embodiment, the bond sites are first trace ends of a plurality of signal traces, some of the signal traces extending in an outward direction away from the die-attach region into a signal trace region, and some of the signal traces being directed within the intermediate region. Signal vias are formed in both the signal trace region and the intermediate region, and are electrically coupled to the signal traces at second trace ends of the signal traces. Formed on the other side of the circuit board, are solder bumps (solder balls) corresponding to the signal vias. By directing some of the signal traces into the intermediate region, board space is made available in the signal trace region so that signal traces can be fabricated without exceeding minimum pitch limitations. At the same time, the additional traces formed within the intermediate region provide additional signal paths to accommodate integrated circuit dies having high a number of I/O pads. |
