Microcomputer with detection of predetermined data for enabling execution of instructions for stopping supply of clock

摘要

A microcomputer comprising an exclusive register 61, an STP/WIT instruction valid/invalid control circuit 60 which detects that data are written consecutively in the register 61 and that values of the data are in a predetermined combination, and AND gates 11 and 12 which permit execution of the STP instruction and the WIT instruction for stopping clock phi only when the predetermined signal is outputted from the STP/WIT instruction valid/invalid control circuit 60, and capable of avoiding the instruction for stopping the internal clock being executed by mistake.