发明名称 |
Regulated supply for voltage controlled oscillator |
摘要 |
A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a voltage controlled oscillator (VCO) which has two differential transconductors. The second differential transconductor has a positive input coupled to a positive output of the first differential transconductor, a negative input coupled to a negative output of the first differential transconductor, a positive output coupled to a negative input of the first differential transconductor, and a negative output coupled to a positive input of the first differential transconductor. Each differential transconductor has a negative output impedance. Each differential transconductor includes a current controlled transconductor circuit (CCXG) and a voltage-current converter coupled to a first supply node for providing a current to the CCXG responsive to a voltage applied to a voltage control input of the differential transconductor.
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申请公布号 |
US5686867(A) |
申请公布日期 |
1997.11.11 |
申请号 |
US19960657087 |
申请日期 |
1996.06.03 |
申请人 |
MARVELL SEMICONDUCTOR, INC. |
发明人 |
SUTARDJA, PANTAS;SUTARDJA, SEHAT |
分类号 |
H03K3/0231;H03L7/089;H03L7/099;(IPC1-7):H03L5/00 |
主分类号 |
H03K3/0231 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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