Multiple-bank memory architecture and systems and methods using the same

摘要

A memory 20 is disclosed including a first column of memory cells including a conductive bitline 202 and a second column of memory cells also including a conductive bitline 202. A gate 203 is provided for selectively coupling the bitline 202 of the first column with the bitline 202 of the second column for transferring a bit of data from a selected cell of the first column to a selected cell of the second column.