发明名称 High speed, reduced power memory system implemented according to access frequency
摘要 A memory system including a first memory area (MEM-A) implemented using memory units including low threshold voltage transistors powered by a low supply voltage source, and a second memory area (MEM-B) implemented using memory units including higher threshold voltage cells powered by a higher supply voltage source. The first memory area, MEM-A, is designated to contain frequently accessed variables, with less frequently accessed variables designated for storage in the second memory area, MEM-B. The most frequently accessed variables stored in MEM-A provide for fast access at a low power per access power dissipation level due to the lower supply voltage and lower threshold voltage design. Alternatively, the less frequently accessed variables stored in MEM-B require a high power per access, but negligible leakage current during static steady state conditions.
申请公布号 US5687382(A) 申请公布日期 1997.11.11
申请号 US19950473761 申请日期 1995.06.07
申请人 HITACHI AMERICA, LTD. 发明人 KOJIMA, HIROTSUGU;SASAKI, KATSURO
分类号 G06F12/06;G06F13/42;G11C11/00;(IPC1-7):G06F1/32;G11C11/40 主分类号 G06F12/06
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