发明名称 |
Memory system for processing of digital video signal |
摘要 |
The memory system accesses data in block units, and contains a recognition arrangement for detecting, whether the memory system should execute a read/write process in a full-pixel mode or a half-pixel mode. A control arrangement is provided for controlling the access on data in a unit of blocks of m times n bits, if the recognition arrangement recognizes that the system should work in the full-pixel mode or the access on data in a unit of blocks of m+1 times n+1 bits, if it recognizes that the system should work in half-pixel mode at an read access. A block of 16 times 16 bits is preferably accessed in the full-pixel modus.
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申请公布号 |
DE19648060(A1) |
申请公布日期 |
1997.11.06 |
申请号 |
DE19961048060 |
申请日期 |
1996.11.20 |
申请人 |
LG SEMICON CO., LTD., CHEONGJU, KR |
发明人 |
CHOI, GO HEE, CHUNGCHEONGBUK, KR |
分类号 |
G06F12/06;G06F12/00;G09G5/00;G09G5/39;G11C7/00;G11C7/10;H04N5/14;H04N5/907;(IPC1-7):G06T1/60;H04N1/40 |
主分类号 |
G06F12/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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