A FLUORINATED OXIDE LOW PERMITTIVITY DIELECTRIC STACK FOR REDUCED CAPACITIVE COUPLING

摘要

A low permittivity interlevel structure comprising a dielectric formed on the topography of a semiconductor substrate. The dielectric comprises a lower region proximal to the semiconductor substrate, an intermediate region comprised of an oxide into which fluorine is incorporated in an atomic concentration of approximately four to ten percent, and an upper region. A method of forming the dielectric structure includes forming a first interconnect level on a substrate. A first dielectric layer, preferably a CVD oxide, is formed on the topography defined by the first interconnect and the substrate. A second dielectric layer, having a dielectric constant lower than the first dielectric layer, is then formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. The second dielectric layer is preferably formed in a CVD chamber from a silane or TEOS source and a fluorinating material such as SiF4.