Digital phase locked loop for clock recovery

摘要

The PLL (10) includes two frequency dividers (11,12) which receive a reference clock signal of frequency Fref and generate two signals of frequency Fref/M and Fref/N. These signals are applied to an XOR gate (13) which compares their frequencies. The error signal generated by the OR gate is applied to a third frequency divider (14) which also receives a signal of frequency Fol from a local oscillator. The divider generates a signal of frequency Fk which is applied to a mixer (15) which also receives a fixed frequency signal (Fo) from an adder (16).