发明名称 FERROELECTRIC MEMORY
摘要 PROBLEM TO BE SOLVED: To realize ferroelectric memories such as shadow RAM and so forth capable of raising S/N in respective modes simultaneously and also setting its capacitive coupling ratios easily. SOLUTION: At the time of a recall mode, high levels are supplied to electrodes of other sides of capacitors Csa, that is, to plate lines PL0a∼PLma and low levels are supplied to electrodes of other sides of capacitors Csb, that is, to plate lines PL0b∼PLmb and at the time of a read or write mode by a volatile mode, low levels of the same potentials are supplied to these plate lines. Thus, coupling ratios at the time of a recall operation are made large by making capacitors Csb act as load capacitances and at the time of the volatile mode, capacitive coupling ratios at the time of a normal readout operation are made small by making capacitors Csb act as information storage capacitances.
申请公布号 JPH09288893(A) 申请公布日期 1997.11.04
申请号 JP19960122396 申请日期 1996.04.18
申请人 HITACHI LTD;HITACHI VLSI ENG CORP 发明人 FUJISAWA HIROKI;NAGASHIMA YASUSHI;HASEGAWA MASATOSHI;NARUI SEIJI;SUZUKI TSUYUKI;AOKI YASUNOBU
分类号 G11C14/00;G11C11/22;G11C11/404;H01L21/8242;H01L21/8246;H01L21/8247;H01L27/10;H01L27/105;H01L27/108;H01L29/788;H01L29/792 主分类号 G11C14/00
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