发明名称 RECEIVING DEVICE
摘要 PROBLEM TO BE SOLVED: To shorten the time from power-on operation to the stabilization of the oscillation frequency of a voltage-controlled oscillation means as to a PLL synthesizer type receiving device. SOLUTION: This device has a 1st storage means 9 which stores data for setting the frequency division value of a 1st frequency dividing means 3, channel by channel, and a 2nd storage means 10 which stores data for setting the frequency division value of a 2nd frequency dividing means 6, channel by channel. Consequently, a reference frequency inputted to a phase comparing means can be set larger than channel intervals, and the time from the power-ON operation to the stabilization of the oscillation frequency of the voltage-controlled oscillation means can be shortened.
申请公布号 JPH09289448(A) 申请公布日期 1997.11.04
申请号 JP19960102372 申请日期 1996.04.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HORIIKE YOSHIO;YOSHIKAWA YOSHISHIGE
分类号 H03L7/107;H03L7/187;H04B1/16 主分类号 H03L7/107
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