发明名称 STORAGE DEVICE AND MEMORY ACCESS CONTROL METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To perform a high-speed access of plural data. SOLUTION: This storage device is provided with memories 4a and 4b where the plural data are stored in an order along with an EC(code for error correction), a detection part 321 for detecting a data error based on the ECC, a correction part 122 for correcting the data error based on a result in the detection part 121, an MPU 8 and a data switching part 11. The MPU 8 successively reads the plural data and the ECCs from the memory, the memory tentatively stores the read data in a built-in register, and then the data are read from the register repeatedly for two times. At this time, the read of a second time is synchronized with the read of a first time of the data to be read next stored in the other register. The data switching part 11 simultaneously transfers the read data of the first time and the second time, respectively to the detection part 121 and the correction part 122.
申请公布号 JPH09288618(A) 申请公布日期 1997.11.04
申请号 JP19960098520 申请日期 1996.04.19
申请人 HITACHI LTD 发明人 TAMURA TAKAYUKI;KATAYAMA KUNIHIRO;NAITO TOSHIYUKI;WATAYA HITOSHI
分类号 G06F12/16;G06F11/10 主分类号 G06F12/16
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