发明名称 AND-OR-NOT COMBINATION TRIGGER CIRCUIT IN BUS INFORMATION PROCESSING UNIT
摘要 The AND-OR-NOT combination trigger circuit in a bus information processing unit provides the bus information processing unit with a combination trigger circuit which includes AND logic, OR logic, and NOT logic in each trigger condition, so as to effectively perform data detection. The AND-OR-NOT combination trigger circuit includes a reference cell consisting of a predetermined number of logic devices to satisfy a desired detecting trigger condition by AND-OR-NOT combination and a common cell consisting of a predetermined number of logic devices to satisfy a desired detecting trigger condition.
申请公布号 KR0120716(B1) 申请公布日期 1997.11.04
申请号 KR19940007770 申请日期 1994.04.13
申请人 KOREA ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 HAN, JONG-SUK;SONG, YONG-HO;KI, AHN-DO;YUN, SUK-HAN
分类号 H03K19/20;(IPC1-7):H03K19/20 主分类号 H03K19/20
代理机构 代理人
主权项
地址