发明名称 POWER CONSUMPTION REDUCING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To more effectively reduce power consumption by deciding and supplying the combination of an operation frequency and operation voltage, which can operate a system logic. SOLUTION: The input frequency and supply voltage to the system logic 6 is decided by an operation frequency/operation voltage deciding circuit 2. The operation frequency/operation voltage deciding circuit 2 has a function for deciding lowest operation voltage for operating with the desired frequency or a highest operation frequency for operating with desired voltage by using a depending relation between the operation frequency and operation voltage of CMOS LSI. The decided input frequency and supply voltage are supplied to the system logic 6 by a frequency variable oscillation circuit 3 and a voltage variable regulator 4. When power consumption is to be reduced, not only the frequency is lowered but also lowest voltage which can be operated with the frequency is supplied to the system logic 6. Thus, the effect of low power consumption becomes larger.</p>
申请公布号 JPH09288527(A) 申请公布日期 1997.11.04
申请号 JP19960100909 申请日期 1996.04.23
申请人 NEC CORP 发明人 YAMASHITA TOSHITSUGU
分类号 G06F1/32;G06F1/04;G11C11/407;(IPC1-7):G06F1/04 主分类号 G06F1/32
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