| 摘要 |
In order to effectively detect coincidence of consecutively transmitted adjacent data words, a shift register is provided for converting incoming serial data to n-bit parallel data. The serial data includes a plurality of identical words each consisting of n bits. A bit coincidence detector is coupled to the shift register so as to determine if a n-stage shifted bit of a given word coincides with a bit which is included in a word subsequent to the given word and which corresponds to the n-stage shifted bit. The bit coincidence detector generates a coincidence check bit which indicates a bit coincidence result. Both the n-bit parallel data and the coincidence check bit are latched after each word has been converted to corresponding parallel data.
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