| 摘要 |
An integrated structure is provided that includes a DRAM cell with a trench storage capacitor, and a corresponding storage node precharge circuit. The entire structure ideally requires only eight square features of area per memory bit. The structure also provides a partial leakage current shield for the DRAM storage node diffusion, thereby improving the data hold time. A graded impurity region around the storage node diffusion enhances the leakage shielding effect. The structure can be operated independently as a DRAM leakage shield if the precharge circuit is not needed. In that case, a junction diffusion in the structure can be eliminated and a leakage shielding effect is still achieved.
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