发明名称 |
Semiconductor memory with test circuit |
摘要 |
A test circuit and method for a semiconductor memory array such as a dynamic random access memory (DRAM) or static random access memory (SRAM) array that reduces the required testing time. A row of memory cells is concurrently written to a logic level, then read. Any faulty memory cells will discharge both true and complementary data lines through a diode or a diode-connected FET. The resulting voltage on the data line is less than its precharged high logic level, allowing detection of any faulty memory cell in the row of memory cells.
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申请公布号 |
US5684809(A) |
申请公布日期 |
1997.11.04 |
申请号 |
US19970798848 |
申请日期 |
1997.02.12 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
STAVE, ERIC;WALD, PHILLIP G. |
分类号 |
G11C29/34;(IPC1-7):G06F11/00 |
主分类号 |
G11C29/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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