发明名称 STATIC SEMICONDUCTOR MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To improve the cell ratio by applying different back gate biases corresponding to different voltages to a plurality of insulating gate field-effect transistors and thus generating differences in driving capability of the insulating gate field-effect transistors. SOLUTION: In the operation of a flip-flop circuit of a memory cell, a silicon substrate 1 and an epitaxial layer 2 are biased to a Vcc potential. In addition, a P<+> diffusion layer 3 is biased to a GND potential. Therefore, in a driving MOS transistor including an SO1 channel region 5, a gate insulating film 6, a gate electrode 7 and SOIN<+> regions 9, 10, formed via an insulator layer 4 on the epitaxial layer 2, a back gate bias effect of the transistor is generated and the threshold value is shifted toward a negative value. This amount of shift of the threshold value generates the difference in driving capability between the MOS transistor and a transfer MOS transistor, thereby increasing the cell ratio.
申请公布号 JPH09283640(A) 申请公布日期 1997.10.31
申请号 JP19960084867 申请日期 1996.04.08
申请人 NEC CORP 发明人 KITAKATA MAKOTO
分类号 H01L21/762;H01L21/8234;H01L21/8244;H01L27/088;H01L27/11;H01L27/12;H01L29/786 主分类号 H01L21/762
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