| 摘要 |
PROBLEM TO BE SOLVED: To eliminate the need for adjustment of a frequency division value N by setting automatically the value N so that the sampling number of video signals for one horizontal scanning period is coincident with the number of horizontal pixels of a video display PDP(an example of display panels) thereby extending a range of corresponding horizontal synchronizing frequencies. SOLUTION: In this PLL circuit, a video signal sampling clock is obtained from an output of a VCO 16, a phase difference between the phase of a signal resulting from frequency-dividing the frequency of this clock by 1/N with a frequency divider 24 and the phase of a horizontal synchronizing signal HD is obtained by controlling the VCO 16 by a voltage proportional to the phase difference to obtain the clock synchronized with the HD. In this case, the PLL circuit is provided with an N-value retrieval circuit 22 retrieving the value N to make the sampling number of the video signals for one horizontal scanning period (1H) coincident with the number of horizontal pixels of a PDP, and the N value retrieved by the N-value retrieval circuit 22 is set to the frequency divider 24 as a frequency division number N, then the N value to make the number of samplings of the video signal for 1H coincident with the number of horizontal pixels of the PDP is set automatically as the frequency division value. |
