发明名称 INTERMITTENT OPERATION DELAYED LOCKED LOOP
摘要 PROBLEM TO BE SOLVED: To avoid loss of synchronization caused by fading for a long time and to reduce the power consumption in the case of configuration of a synchronization circuit for the direct spread spectrum communication system. SOLUTION: A desired wave power discrimination means 212 is provided to an output terminal, a sliding correlation device (SC) 204 takes correlation between a signal delaying an output of a reception section 201 by a time ΔTc and a spread code of a receiver outputted from a spread code generator 211 to detect a level of a synchronized desired wave. When the level is lower than a prescribed level, the operation of a delay circuit 203, SCs 205, 206, level detectors 207, 208 and an adder 209 is stopped to bring the operation of a phase locked loop PLL 210 into a flywheel operation and when the level is higher than the prescribed level, the operation stop is released to activate the PLL 210 normally.
申请公布号 JPH09284178(A) 申请公布日期 1997.10.31
申请号 JP19960120796 申请日期 1996.04.19
申请人 KOKUSAI ELECTRIC CO LTD 发明人 MIYATANI TETSUHIKO
分类号 H03L7/14;H04B1/707;H04B1/7085;H04B7/01;H04L7/033 主分类号 H03L7/14
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