发明名称 CLOCK GENERATOR
摘要 PROBLEM TO BE SOLVED: To miniaturize a generator through reduction in umber of circuits and a simple configuration by generating reference and display clocks phase- locked to either of a frequency division signal of a system clock or a horizontal synchronizing signal depending on a display mode. SOLUTION: An operation system clock outputted from a crystal oscillation circuit 16 is fed to a frequency divider circuit 17, which generates a horizontal reference signal HS. A horizontal synchronizing signal H is fed to an input terminal 18. Then the signal HS or H is given selectively to a phase comparator circuit 20 by a switch circuit 19 depending on a display mode. On the other hand, an output signal of a VCO 25 is fed to the circuit 20 via a frequency divider circuit 26, the circuit 20 compares phases of the received signals and its output signal is fed to a loop filter 28 and its output is fed to a circuit 25 as a voltage to control the oscillated frequency. The oscillated output from the circuit 25 is extracted from an output terminal 29 as a reference clock and the oscillated output of the circuit 25 is frequency-divided by a frequency divider circuit 30, thereby its output is extracted from an output terminal 31 as a display clock.
申请公布号 JPH09284131(A) 申请公布日期 1997.10.31
申请号 JP19960086683 申请日期 1996.04.09
申请人 TOSHIBA CORP 发明人 KOSAKA YOSHIAKI
分类号 H04N5/06;G09G5/12;G09G5/22;H03L7/14 主分类号 H04N5/06
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