发明名称 DECODER AND DECODING METHOD
摘要 <p>PROBLEM TO BE SOLVED: To limit an arithmetic operation amount in the case of decoding depending on the capability of the hardware by limiting a range of an upper limit and a lower limit of filters in use in frequency synthesis depending on the performance of the hardware to execute filter processing. SOLUTION: A frequency synthesis filter bank 4 conducts filter processing within a range set by a setting means 5. A hardware performance information table 6 stores the performance of the hardware of decoders and a setting range of filters capable of processing corresponding to the hardware as a table. Based on the hardware performance information of a decoder, the means 5 refer the hardware performance information table 6 to set a range of filters capable of processing in the frequency synthesis filter bank 4. Concretely the means 6 sets an upper limit filter and a lower limit filter in the frequency synthesis filter bank 4 depending on the arithmetic parformance hardware of the decoder.</p>
申请公布号 JPH09284137(A) 申请公布日期 1997.10.31
申请号 JP19960092653 申请日期 1996.04.15
申请人 NEC CORP 发明人 ISHINO TOSHIYUKI
分类号 H03M7/00;H03M7/30;H04J99/00;H04N7/24;H04N19/00;H04N19/117;H04N19/134;H04N19/189;H04N19/635;(IPC1-7):H03M7/30;H04J15/00 主分类号 H03M7/00
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