| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the number of parts at the clock oscillator of a circuit having plural clock systems and to easily reduce clock skew in the case of operations at the same frequency by providing a frequency divider with which a clock signal to be supplied to a flipflop is defined as an input signal, a frequency dividing ratio is programmably set and a compare signal to a phase comparator is outputted. SOLUTION: A reference clock signal (frequency fs) is branched and inputted to phase comparators 9a and 9b. At the clock system of a random logic 15a, a phase locked loop circuit is constituted by using the phase comparator 9a, loop filter 11a, voltage controlled oscillator 12a, clock tolly 13a, flip-flop 14a and frequency divider 8a and a transmission frequency can be set at fs*Na by changing a frequency dividing ratio Na of the frequency divider 8a. Similarly, the clock system of a random logic 15b can be operated at a transmission frequency fs*Nb different from that of the random logic 15a by changing a frequency dividing ratio Nb of a frequency divider 8b.</p> |
