| 摘要 |
PROBLEM TO BE SOLVED: To accelerate the fetching speed of a plotting command from a FIFO and to provide a high-speed graphic processor. SOLUTION: The FIFO for holding the plotting command from a host PC is mapped to the RFIFO space A and RFIFO space B of the cachable space of an MPU for processing the plotting command. At the time of fetching the plotting command from the RFIFO, in the case of performing it through the space A, the MPU instructs the read addresses of the respective blocks of the space A in an order, instructs a space flag different from the tag field of a cache, intentionally generates a cache error and fetches the plotting command from the FIFO to the cache at the time. For the fetching of a processing program, a value same as the space flag of the cache after the fetching of the RFIFO space A is instructed and a cache hit is performed at all times. The RFIFO space A and the RFIFO space B are alternately read. |
