SEMICONDUCTOR MEMORY APPARATUS

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus having an SRAM cell which can reduce a column current when data are read, decrease consumed power and stabilize holding of data. SOLUTION: A reference voltage generated at a Vref1 generation circuit 16 is supplied to a back gate of an access transistor of each SRAM cell constituting columns selected by a column decoder 2 from a corresponding application selector. Meanwhile, a substrate voltage generated at a Vbb generation circuit 14 is supplied from a corresponding application selector to a back gate of an access transistor of each SRAM cell constituting columns not selected by the column decoder 2.