| 摘要 |
PROBLEM TO BE SOLVED: To suppress jitter increased due to a ratio by reducing the ratio of an input signal frequency of a phase detector to an oscillated frequency of a voltage controlled oscillator(VCO). SOLUTION: The Phase Locked Loop(PLL) circuit 1 is configured by connecting PLL means 2, 3 in series which are provided with prescaler frequency dividers 2a, 3a which factorize a frequency division ratio to obtain a prescribed oscillated frequency from VCOs 2d, 3d based on a received clock and select the frequency division ratio by the factorized factor and feedback frequency dividers 2f, 3f. Furthermore, The frequency division rate for the prescaler frequency divider 2a and the feedback frequency divider 2f of the PLL means 2 is fixed in common and the frequency division rate for the prescaler frequency divider 3a and the feedback frequency divider 3f of the PLL means 3 is set variable depending on a sampling frequency. |
