发明名称 EXCLUSIVE OR CIRCUIT
摘要 An exclusive OR circuit includes first and second inverters, a PMOS transistor MP3 in which the output of the first inverter is connected to its gate and DC voltage is applied to its source, an NMOS transistor MN3 in which the output of the first inverter is connected to its gate and the output of the second inverter is connected to its source, a PMOS transistor MP4 in which the output of the second inverter is connected to its gate and its source is connected to the drain of MP3, an NMOS transistor MN4 in which the output of the second inverter is connected to its gate and the output of the first inverter is connected to its drain, an input section 20 through which the outputs of MN3, MN4 and MP4, connected by one output line, are output, a PMOS transistor MP5 in which the output of the input section is connected to its gate and DC voltage is applied to its source, an NMOS transistor MN5 in which the output of the input section is connected to its gate and its source is grounded, a first bipolar transistor Q1 in which its base is connected to the drain of MP5 and DC voltage is applied to its collector, and a second bipolar transistor Q2 in which its base is connected to the drain of MN5 and its collector is grounded, the first and second bipolar transistors constructing an output section 21.
申请公布号 KR0120600(B1) 申请公布日期 1997.10.30
申请号 KR19940028586 申请日期 1994.11.02
申请人 LG SEMICONDUCTOR CO.,LTD 发明人 PARK, KYUNG-AH
分类号 H03K19/21;(IPC1-7):H03K19/21 主分类号 H03K19/21
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