发明名称 Sync detection circuit and method using variable reference for comparison with mismatch count
摘要 In a sync detector, a baseband signal is segmented into a plurality of successive bit sequences so that the bits of each sequence are shifted by one bit position with respect to the bits of adjacent sequences. On a bit-by-bit basis, mismatches are detected between each input bit sequence and a predetermined bit sequence and the detected mismatches are counted to produce a mismatch count. A first comparison is made between the mismatch count and a reference value to determine that a sync code is detected if the mismatch count is equal to or smaller than the reference value, and a further comparison is made between successively produced mismatch counts to determine that a sync code is detected when the later of the successively produced mismatch counts is equal to or smaller than the earlier one. The first comparison is repeated when the later mismatch equals zero.
申请公布号 AU1911197(A) 申请公布日期 1997.10.30
申请号 AU19970019111 申请日期 1997.04.24
申请人 NEC CORPORATION 发明人 KAZUO MORITA
分类号 H04L7/08;H04L7/04;H04Q7/14 主分类号 H04L7/08
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