| 摘要 |
<p>A frequency multiplier includes a set of substantially identical inverters (G1-G8) connected in series for successively delaying an input periodic reference signal (T0) to produce a set of inverter output signals. A phase controller (14, 18) adjusts the delay provided by each inverter so that the output signal of a last inverter (T8) of the series is phase-locked to a reference signal supplied as input to the first inverter of the series. Thus, the inverter outputs are evenly distributed in phase with pulse edges evenly dividing the period of the reference signal. A set of XOR gates (X1-X3) logically combine selected inverter output signals to produce periodic output signals of frequencies which are even multiples of the reference signal.</p> |
