Clock Generation

摘要

Clock generation circuitry comprises: a plurality of sequentially connected delay devices (Do-D5), a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device; control means (14) common to said delay devices for controlling said predetermined time interval; and output means (16) coupled to receive the output signals of the delay devices to produce therefrom said second clock signal. <IMAGE>