Increasing testability by clock transformation

摘要

A method of increasing the testability of sequential circuit designs uses a clock transformation technique. Circuit states which are difficult to reach, but are nonetheless required to detect at least one fault of the circuit, are automatically identified. By way of illustration, estimations of joint line probabilities are compared with a preselected threshold value to identify hard-to-reach states. Then, commonly clocked flip-flops (18) which must be simultaneously assigned values in order to reach the identified states are partitioned into independently clocked (via TEST CONTROL INPUTS) groups of flip-flops. In this manner, hard-to-reach circuit states are transformed into easy-to-reach states, which, in turn, results in transforming difficult-to-detect faults into easy-to-detect faults.