VARIABLE LENGTH PAIR CONVERTING CIRCUIT FOR J-PEG ALGORITHM

摘要

A variable length pair converting circuit for JPEG algorithm is capable of encoding process and decoding process by a single circuit. The variable length pair converting circuit for JPEG algorithm for encoding and decoding a variable length pair in a variable length code module complying with the regulation of JPEG (Joint Photographics Experts Group) includes a first barrel shifter(1) for controlling an effective bit number of an input data in response to a control signal provided from the variable length code module, a second barrel shifter(2) having one input terminal connected to an output terminal of the first barrel shifter and the other input terminal to receive data provided from the variable length code module, for controlling a code length of the data inputted through one of the two input terminals in response to a control signal provided from the variable length code module, a code detector(3) for determining a code of an amplitude from the output data of the second barrel shifter in decoding; an absolute value-compliment converting circuit(4) for converting the amplitude coded in a form of compliment of 1 provided from the second barrel shifter in decoding, and converting the amplitude of the absolute value inputted in an RLD (Run Length Code) form to a complimentary form of 1; a first bit inverse arrangement circuit(5) for arranging the amplitude of the RLC inputted from the variable length code module in a inverse order in encoding and providing it to the absolute value-complement converting circuit; and a second bit inverse arrangement circuit(5a) for rearranging the output data from the second barrel shifter in a inverse order.