| 摘要 |
<p>A self-clocked apparatus for eliminating race condition in high speed decoders is provided. In multi-stage decoders, a first stage is generally composed of predecoder blocks while a second stage is generally composed of decoder/driver blocks. Each predecoder block receives several address bits and outputs a high or low level signal depending on the address bits state. Each decoder/driver block receives the output signal of the corresponding predecoder block, and outputs a signal selecting or not selecting a connected line. The self-clocked apparatus of the invention is cross-connected between adjacent predecoder blocks such that the ith decoder/driver block is controlled by the i + 1th predecoder block, and conversely. No external clock signal is used, and no time margins is required. Furthermore, the invention provides a robust electrical design. <IMAGE></p> |
