发明名称
摘要 PURPOSE:To prevent the breakdown of a data processor and to improve its reliability by prefetching again an instruction out of an erroneous instruction via an instruction prefetching circuit in case the occurrence of an error is not detected by a detecting means and not stored in a storing means yet. CONSTITUTION:An arithmetic process holding circuit 4 detects the occurrence of a correctable error of an arithmetic processing circuit 2 and the detection of said error occurrence is not stored in an error indicator. In such a case, an instruction prefetching circuit 1 prefetches again an instruction out of the instruction given when the circuit 2 has a correctable error in a transfer mode. Thus the circuit 2 can receive an instruction when it has a correctable error. Thus, it is possible to prevent the breakdown of a data processor and to improve the reliability of this processor.
申请公布号 JP2671305(B2) 申请公布日期 1997.10.29
申请号 JP19870150585 申请日期 1987.06.17
申请人 发明人
分类号 G06F11/14;G06F9/38 主分类号 G06F11/14
代理机构 代理人
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