| 摘要 |
<p>A display comprises a liquid crystal panel, a signal line driver circuit for generating a signal, which is to be supplied to a signal line, on the basis of image data and a first clock signal CK1, a control signal generating circuit (12) for generating the first clock signal CK1 and a regulating clock signal SCK on the basis of a reference clock signal, and a delay time regulating circuit (14) for delaying data by a predetermined time on the basis of the regulating clock signal SCK from the control signal generating circuit (12) for the purpose of regulating the delay time of the first clock signal CK1 generated with respect to the data by the control signal generating circuit (12). The delay time regulating circuit (14) is provided with a PLL circuit (16) for correcting the regulating clock signal SCK, and a PLL circuit (34) for correcting the first clock signal CK1 supplied to the signal line driver circuit, whereby the phase of the first clock signal CK1 and that of the data are accurately set in agreement with each other. <IMAGE></p> |
