发明名称 |
Deadlock avoidance for switched interconnect bus systems |
摘要 |
A deadlock avoidance system for avoiding interconnection deadlocks between a plurality of data transfer devices includes a controller, a switch interconnector coupled to all of said data transfer devices for interconnecting on a one-to-one basis selected ones of the data transfer device as requesting units to selected ones of said data transfer devices as receiving units. A transfer queue is employed that includes a master transfer register and a slave transfer register, a master register, a slave register and a target register.
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申请公布号 |
US5682485(A) |
申请公布日期 |
1997.10.28 |
申请号 |
US19960692988 |
申请日期 |
1996.08.07 |
申请人 |
UNISYS CORPORATION |
发明人 |
FARMER, MICHAEL EDWARD;MURPHY, STEVEN ALLEN;STEVENS, RICK CLEVIE |
分类号 |
G06F13/362;G06F13/40;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/362 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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