发明名称
摘要 PURPOSE:To permit the same basic information to be shared, by controlling connection or disconnection between a first address bus and a first data bus connected to a main processor, and a main memory, and between a second address bus and a second data bus connected to a frame buffer. CONSTITUTION:A bus switch 20 switches the supplying of the address buses of the main memory 12 and the frame buffer 14 from which address bus connected to a graphic processor 10, or a central processor 11. The graphic processor 10 which becomes a second processor means receives a command, and a bit of parameter information transferred from the central processor 11 which becomes a first processor means, or a main memory 12, and accesses to the frame buffer 14, or the main memory 12, and generates a character, or a graphic data. Also, the graphic processor 10 can read out the command, or the bit of parameter information also from the frame buffer 14.
申请公布号 JP2667817(B2) 申请公布日期 1997.10.27
申请号 JP19860236148 申请日期 1986.10.06
申请人 发明人
分类号 G06F3/153;G06F15/16;G06F15/167;G06T11/00;G06T11/20;(IPC1-7):G06F15/16 主分类号 G06F3/153
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