A video image data decoding apparatus is disclosed which comprises a pair of buffer memories for storing decoded intra coded picture data or forward prediction coded picture data, a switching circuit for causing the decoded intra coded picture data or forward prediction coded picture data to be sequentially stored in the pair of buffer memories, and a generation circuit utilizing picture data stored in one buffer memory of the pair of buffer memories for generating picture data to be stored into another buffer memory and also utilizing picture data stored in one buffer memory for generating picture data to be newly stored into the same buffer memory. The generation circuit performs motion compensation when the same utilizes picture data stored in one buffer memory for generating picture data to be stored into another buffer memory, while the same is forbidden to perform motion compensation within a predetermined range when the same utilizes picture data stored in one buffer memory for generating picture data to be newly stored into the same buffer memory. <IMAGE>
申请公布号
DE69222240(D1)
申请公布日期
1997.10.23
申请号
DE1992622240
申请日期
1992.07.08
申请人
SONY CORP., TOKIO/TOKYO, JP
发明人
VELTMAN, MARK, C/O SONY CORP., SHINAGAWA-KU, TOKYO, JP;YONEMITSU, JUN, C/O SONY CORP., SHINAGAWA-KU, TOKYO, JP