The means is of a data protecting means (310) for preventing erroneous writing in a data-holding circuit (307). A data protecting circuit (311) receives a data protect set/release select signal Sa outputted from a processor (330) and starts a second clocking means (316). When the second clocking means (316) measures a period T2, the data protecting circuit (311) detects the level of a chip select signal CS produced by a power source monitoring circuit (320) and sends a data protecting signal DP corresponding to the level of the signal Sa to a data-holding circuit (307) only when a main power source (305) is judged to be normal.
申请公布号
DE68928324(D1)
申请公布日期
1997.10.23
申请号
DE1989628324
申请日期
1989.12.19
申请人
OKI ELECTRIC INDUSTRY CO., LTD., TOKIO/TOKYO, JP;OKI MICRO DESIGN MIYAZAKI CO. LTD., MIYAZAKI, JP
发明人
ARAI, YASUO OKI ELECTRIC INDUSTRY CO., LTD., TOKYO 105, JP;SATO, HISATAKE OKI MICRO DESIGN MIYAZAKI CO.,LTD., MIYAZAKI 880, JP