发明名称
摘要 PURPOSE:To reduce the number of the wirings connecting a package to be monitored and a monitor package. CONSTITUTION:In a monitor package 31, a pulse generating circuit 32 generates a clock pulse 35 and a frame pulse 36 and these pulses are distributed to a plurality of packages 11, 21 to be monitored. In the packages 11, 21 to be monitored, counters 12, 22 count the clock pulse 35 so as to be synchronous to the frame pulse 36 in phase to output counter output signals 15, 25. Comparing circuits 16, 26 compare the count values of the counter output signals 15, 25 with the numbers showing package mounting position indicating input signals 16, 26 indicated at every mounting position. Output circuits 14, 24 output a logical 'L' level to time slots wherein the count values and the numbers coincide at the time of mounting under three-state control and serially multiply the level to send out the same to a signal bus 37. The serially multiplied signal is separated by the separation circuit 33 of the monitor package 31 to obtain a state signal 39.
申请公布号 JP2666579(B2) 申请公布日期 1997.10.22
申请号 JP19910022635 申请日期 1991.01.24
申请人 发明人
分类号 G01R31/00;H04B17/00 主分类号 G01R31/00
代理机构 代理人
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