| 摘要 |
<p>A semiconductor memory device comprises: a matrix (50) of memory cells comprising a plurality of rows (WL) of memory cells; first means (13) for generating a first internal timing signal (ATD) activated upon changing of a current address (ADD) supplied to the memory device, the first timing signal remaining activated for a prescribed time substantially at the beginning of a read cycle of the memory device; row address decoding means (4) supplied by the current address (ADD) for selecting a row of memory cells; second means (RR1-RR4,3,1) for storing defective addresses of defective rows in the matrix of memory cells, for comparing the defective addresses with a current address supplied to the memory device, for selecting a redundancy row (RW1-RW8) when the current address coincides with one of the defective addresses and for correspondingly deactivating the row address decoding means to prevent the selection of the defective row. The memory device comprises redundancy control means (5) supplied by the first timing signal (ATD), the redundancy control means enabling said row address decoder means at the beginning of the read cycle independently of the current address and maintaing the row address decoder means enabled until the first timing signal is deactivated. <IMAGE></p> |
