| 发明名称 |
Circuit and method for accessing memory cells of a memory device |
| 摘要 |
A circuit and method for concurrently addressing at least two rows of memory cells of a memory array of a memory device. By concurrently addressing at least two rows of memory cells during testing of the memory device during a burn-in period, the memory device can be tested in a reduced time period.
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| 申请公布号 |
US5680362(A) |
申请公布日期 |
1997.10.21 |
| 申请号 |
US19960657637 |
申请日期 |
1996.05.30 |
| 申请人 |
UNITED MEMORIES, INC.;NIPPON STEEL SEMICONDUCTOR CORPORATION |
发明人 |
PARRIS, MICHAEL C.;BUTLER, DOUGLAS B.;HARDEE, KIM C. |
| 分类号 |
G11C11/413;G11C8/12;G11C11/401;G11C11/407;G11C29/00;G11C29/06;G11C29/34;G11C29/46;(IPC1-7):G11C8/00;G11C7/00 |
主分类号 |
G11C11/413 |
| 代理机构 |
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