发明名称 |
Interconnect failure detection and cache reset apparatus |
摘要 |
A system for resetting a cache in a first device connected by a multilinelink to a memory in a second device. A transceiver in the first element connects to one end of each of the link lines and a transceiver in the second device connects to the other end. The transmitter in the first device transceiver is disabled in response to a failure of the transceiver to receive messages from the second device. The transmitter in the first device transceiver also selectively sends a reset sequence to the receiver in the second device. A detector detects when all of the receivers in the second device have either received a reset sequence or have detected that a transmitter in the first device is disabled. The detector sets a latch in response, representing that data in the second device cache is invalid. Optionally, the second device has responders which send responses over the link lines indicating receipt of a reset sequence. The transmitters in the first device switch to a disabled state when the responses are not received within a specified period.
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申请公布号 |
US5680575(A) |
申请公布日期 |
1997.10.21 |
申请号 |
US19950443293 |
申请日期 |
1995.05.17 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BARTOW, NEIL GEORGE;CAPOWSKI, ROBERT STANLEY;FASANO, LOUIS THOMAS;GREGG, THOMAS ANTHONY;SALYER, GREGORY;WESTCOTT, DOUGLAS WAYNE |
分类号 |
G06F13/12;G06F15/17;G06F15/173;H04J3/06;H04L7/10;H04L29/06;H04L29/08;H04L29/14;(IPC1-7):G06F13/14 |
主分类号 |
G06F13/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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