Semiconductor memory capable of transferring data at a high speed between an SRAM and a DRAM array

摘要

In an operation of transferring data between a DRAM array and an SRAM array through a bidirectional transfer gate circuit, data blocks on a selected one in the DRAM array are sequentially selected in a high speed mode, word lines are sequentially selected in the SRAM array, so that data is transferred in a time division multiplexing manner between the DRAM array and the SRAM array in units of data block. A cache block size in a semiconductor memory device containing a cache can be externally changed depending on the application with the internal configuration maintained unchangedly.