| 摘要 |
PROBLEM TO BE SOLVED: To sufficiently ensure the margin of characteristics between multilevels without increasing cell transistor size, by installing a plurality of transistors different in current driving capability wherein effective channel width is set to be three or more kinds. SOLUTION: In a first transistor Tr1, implantation of impurity ions for data writing is not performed at all in the channel width region. In a second transistor Tr2, the implantation is performed on the single side surface of a trench part of a silicon substrate, and the effective channel width is about 4/5 of Tr1. In a third transistor Tr3, the implantation is performed on both side surfaces of the trench part of the silicon substrate, and the effective channel width is about 3/5 of Tr1. In a fourth transistor Tr4, the implantation is performed on the upper surface part of the silicon substrate put between the trench parts, and the effective channel width is about 2/5 of Tr1. A plurality of transistors whose effective channel width is set to be three or more kinds such as Tr1, Tr2, Tr3 and Tr4 are installed. Thereby margin between multilevels can be increased in the cell size equivalent to the conventional mask ROM. |
