发明名称 |
Process of forming miniature pattern well controlled in thickness on semiconductor wafer through selective electroplating |
摘要 |
A mask layer is formed on a conductive layer covering not only a central area assigned to integrated circuits but also a vacant peripheral area of a semiconductor wafer, and an electroplating system allows metallic miniature patterns to grow on the conductive layer over the vacant peripheral area as well as extremely small areas of the conductive layer over the central area so as to make current fluctuation negligible.
|
申请公布号 |
US5679234(A) |
申请公布日期 |
1997.10.21 |
申请号 |
US19950530424 |
申请日期 |
1995.09.19 |
申请人 |
NEC CORPORATION |
发明人 |
IMAMURA, TAKAFUMI |
分类号 |
C25D5/02;C25D7/12;H01L21/288;H01L21/3205;H01L21/768;(IPC1-7):C25D5/02;C25D5/54;H01L21/465 |
主分类号 |
C25D5/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|