| 摘要 |
In a demultiplex circuit and an analog-to-digital converter using the demultiplex circuit, since the reset means for controlling the phase of the second clock output from the frequency divider circuit is provided, it is possible to establish the phase of the second clock to establish the output timing of the demultiplex circuit. In addition, since the reset means for controlling the phase of the second clock output from the frequency divider circuit, it is also possible to establish the phase of the second clock to establish the output timing of the analog-to-digital converter.
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